詳細資料
|
[時間更正] 1/19邀請Dr. Vijaykrishnan Narayanan來系演講，請大家踴躍參加
各位老師、同學： 地點： 資工系4210室 內容摘要： Performance and power are the first order design metrics for Network-on-Chips (NoCs) that have become the de-facto standard in providing scalable communication backbones for multicores/CMPs. In this talk, I will present an overview of several design optimizations aimed at improving the performance and power efficiency of on-chip routers. First, I will show the benefits of designing routers using 3D stacked technology. Second, I will show the use of hybrid topologies in enhancing the power and performance efficiencies in a NoC. Finally, I introduce an approach that tunes the frequency of a router in response to network load to manage both performance and power. 個人簡介： Vijaykrishnan Narayanan is currently at the Computer Science and Engineering and Electrical Engineering Departments at Penn State University. He received his B.E. from University of Madras, in 1993 and Ph.D from University of South Florida 1998, respectively. He is a member of the Embedded and Mobile Computing Design Center and his research/teaching interests are in the areas of energy-aware reliable systems, embedded systems, on-chip networks, system design using emerging technologies (3D and Nano) and computer architecture. His research is supported by grants from National Science Foundation, The Technology Collaborative, and DARPA. Dr. Narayanan is actively involved with various technical service activities. He served as general co-chair, ISVLSI 2002; general-chair, ISVLSI 2003; vice-general chair, Nanonets 2007, and as program co-chair for GLSVLSI 2006, Nanonets 2006, and ISLPED 2007. He serves on the steering committees of ISVLSI and GLSVLSI conferences.
相關網址：無 |