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1/15 (五) 資訊系專題演講
Department of Electrical and Computer Engineering University of Illinois at Urbana-Champaign Abstract With on-chip minimum feature size down to nanometer range, there are substantial challenges to the design and manufacturing of VLSI circuits. In the current 45nm technology node, manufacturing process variations have become a major factor that affects circuit performance and could lead to excessive yield loss. This manufacturability problem will get significantly worse in future technology nodes of 32nm/22nm and beyond. In order to cope with manufacturing process variations, a major paradigm shift is required in the way we design VLSI circuits. To handle random variations, we need to develop a new generation of computer-aided design (CAD) software that manipulates statistical random variables rather than deterministic values. To handle systematic variations, we need to develop a new generation of CAD software that understands how these variations are compensated during the down-stream manufacturing steps. In this talk, we give an overview of our contributions in design for manufacturing.
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