05/01(五)邀請Dr. Prashant Saxena來系演講，請大家踴躍參加

各位老師、同學：
系上何宗易老師邀請  ATG, Synopsys, Hillsboro, USA的Dr. Prashant Saxena至系上演講，檢附詳細資訊及時間地點於文後，機會難得，請大家踴躍參加！

主辦單位：國立成功大學 資訊工程系
日 期：5月1日(五)
時 間：2:30pm~4:00pm
地 點：成功大學資訊工程系 4203教室
對 象：資訊及相關系所教師及研究所學生
題 目： The Evolution of Interconnect Management in Physical Synthesis
主講人：Dr. Prashant Saxena  服務單位：ATG, Synopsys, Hillsboro, USA

內容摘要：

With the worsening of interconnects due to scaling, the reliance of the original physical synthesis paradigm on merely some placement of the cells in order to predict net delays no longer suffices. Practitioners have augmented this paradigm over the years with increasingly sophisticated net models in an effort to improve the accuracy of the interconnect delay predictions. In this paper, we will review these advances and motivate their natural evolution towards “guaranteed” net delays by describing a new scheme known as “persistence”. Although a naïve implementation of persistence can result in unroutable circuits, we will describe how persistence can be applied intelligently in an industrial flow to improve the circuit optimization without impacting its congestion.

個人簡介：

Prashant Saxena received the B.E. (Hons.) degree in electrical and electronic engineering and the M.Sc. (Tech.) degree in computer science from Birla Institute of Technology and Science, Pilani, India, in 1991 and the Ph.D. degree in computer science from the University of Illinois at Urbana–Champaign, Urbana, in 1998. Since January 2005, he has been a member of the Technical Staff at the Advanced Technology Group at Synopsys, Inc., Hillsboro, OR. Prior to this, he was with the Strategic CAD Labs, Intel Corporation, from 1998 through 2004. He is the author or coauthor of more than 25 papers in journals and conferences, and the specification for the first Virtual Socket Interface Alliance (VSIA) signal integrity standard. His current research interests are in physical synthesis and layout, signal integrity, and process scaling issues. Dr. Saxena has served on the Technical Program Committee for the International Symposium on Physical Design (ISPD), International Symposium on Circuits and Systems (ISCAS), and International Workshop on System-on-Chip for Real-Time Applications (IWSOC), as well as on several National Science Foundation (NSF) design automation panels, and on task forces for the International Roadmap for Semiconductors (ITRS) and the Semiconductor Research Corporation (SRC). He was an invited speaker at several conferences including ISPD’03, a panelist at ISPD’04, and a tutorial presenter at the Design, Automation and Test in Europe Conference (DATE’05). He was awarded the Intel Architecture Group Trailblazer Award in 2000 and the Best Paper Award at Intel’s internal technical conference in 2003.

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公告人員：系辦人員
公告日期：2009-04-26
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