[學術活動]9/21邀請Dr. Igor L. Markov來系演講，請大家踴躍參加
成大資訊工程專題演講 主辦單位：國立成功大學 資訊工程系 日 期：9月21日(五) 時 間：2:10pm~3:30pm 地 點：成功大學資訊工程系 4263教室 對 象：資訊、電機相關系所教師及研究所學生
| | | 時段：2007/9/21 2:10pm-3:30pm | 地點： 資工系4263室 | | 題目：Open-source software CAD software (including synthesis, verification, floorplanning, partitioning, placement and routing) | | 主講者：Dr. Igor L. Markov | 服務單位：Dept of EECS, University of Michigan Ann Arbor | | 內容摘要：This talk is about CAD algorithms and design methodologies for extremely large integrated circuits lead to integrated optimizations, such as a unification of partitioning, placement and floorplanning; we have also developed a simultaneous optimization of digital logic and layout by finding and exploiting functional symmetries. Our current work predicts and outlines major changes in how large circuits will be designed in the future. In particular, the dominance of wires over transistors (in terms of delay and power) will lead to devastating global effects, such as buffer flooding --- long wires must be buffered, but the inserted buffers may elongate other wires, thus requiring additional buffers. Such global effects will force a complete merger of logical and physical synthesis, and will also heavily impact micro-architecture. In turn, such a merger necessitates new datastructures that capture both evolving logic and evolving layout, as well as new algorithms to perform such evolution. In our current work, we seek effective solutions to the buffer flood problem, and are developing fully integrated logic and layout optimization at large scale. We are also actively looking at large-scale combinatorial optimization and constraint satisfaction relevant to VLSI applications, such as circuit partitioning and Boolean satisfiability. Our software has been included among CAD tools required for the design of LSI Logic's RapidChip integrated circuits (structured ASICs) and in this context was used to design successful chips at Hewlett Packard, Silicon Graphics, CISCO, Raytheon, Seagate, Fujitsu, Hitachi, 3COM, Nortel Networks, Alcatel, Cryptec and IP Wireless. | | 個人簡介：Igor L. Markov is an associate professor of Electrical Engineering and Computer Science at the University of Michigan. He received his M.A. in Mathematics and Ph.D. in Computer Science from UCLA. Currently he is a member of the Executive Board of ACM SIGDA and a senior member of IEEE. Prof. Markov's interests are in combinatorial optimization with applications to the design and verification of integrated circuits, as well as in quantum logic circuits. Prof. Markov's research contributions include new algorithmic techniques for Boolean satisfiability, hypergraph partitioning, block packing, large-scale circuit layout, synthesis of quantum circuits, as well as quantum-mechanical simulation with compressed matrices. Some of these algorithms lead to order-of-magnitude improvements in practice, and many of them are implemented in software, including open-source projects and major commercial tools. Prof. Markov is an associate editor of the ACM Transactions on Design Automation of Electronic Systems, guest editor of VLSI: The Integration Journal, and the maintainer of the online GSRC bookshelf for fundamental CAD algorithms. He has co-authored more than 120 refereed publications, some of which were honored by the best-paper award at the Design Automation and Test in Europe Conference (DATE) and the IEEE CAS Donald O. Pederson award for best paper in IEEE Transactions on Computer-Aided Design. Additionally, Prof. Markov is the recepient of a DAC Fellowship, an ACM SIGDA Outstanding New Faculty award, an ACM SIGDA Technical Leadership Award, an NSF CAREER award, an IBM Partnership Award, and a Synplicity Inc. Faculty award. Prof. Markov served on program committees of major conferences in Electronic Design Automation, including DAC, ICCAD, DATE, ASPDAC, ISPD, ICCD, GLSVLSI. He was the technical program chair of SLIP 2004, the general chair of SLIP 2005, benchmarking chair of IWLS 2005, and vice-chair for tools and methodologies at ICCD 2005. Prof. Markov graduated three Ph.D. and four M.S. students, and is now working with six graduate students. His students won programming contests and fellowships at DAC 2001, ICCAD 2002, ICCAD 2004, ICCAD 2005, IWLS 2006, ISPD 2007, and have directly contributed to Windows Vista at Microsoft, to the first 4-core Opteron processor at AMD, to IBM's flagship chip design software, and to the Open-Access database infrastructure at Cadence and Si2. Current and former students interned at or are employed by AMD, Amazon.com, Cadence, Calypto, the US Department of Defense, the US Department of Energy, General Electric, Google, IBM, Lockheed Martin, Microsoft, Qualcomm, UC Berkeley, Synplicity, and Toyota Research. |
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公告人員：系辦人員
公告日期：2007-09-14
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